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» On performance limitations of congestion control
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TPDS
1998
64views more  TPDS 1998»
13 years 7 months ago
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors
—Instruction fetching is critical to the performance of a superscalar microprocessor. We develop a mathematical model for three different cache techniques and evaluate its perfor...
Steven Wallace, Nader Bagherzadeh
WSC
2007
13 years 10 months ago
Qualitative simulation of construction performance using fuzzy cognitive maps
The construction process is subject to an array of influences, both from internal and external environments, which makes the process performance uncertain and difficult to predict...
Manjula Dissanayake, Simaan M. AbouRizk
BROADNETS
2007
IEEE
14 years 2 months ago
Cross-layer optimization made practical
Abstract— Limited resources and time-varying nature of wireless ad hoc networks demand optimized use of resources across layers. Cross-layer optimization (CLO) for wireless netwo...
Ajit Warrier, Long Le, Injong Rhee
CONEXT
2008
ACM
13 years 9 months ago
A priority-layered approach to transport for high bandwidth-delay product networks
High-speed organizational networks running over leased fiber-optic lines or VPNs suffer from the well-known limitations of TCP over long-fat pipes. High-performance protocols like...
Vidhyashankar Venkataraman, Paul Francis, Murali S...
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 19 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...