46 search results - page 6 / 10 » On pipelining dynamic instruction scheduling logic |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
CGO
2003
IEEE
14 years 24 days ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
GLVLSI
1997
IEEE
13 years 11 months ago
1997
IEEE
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. Ho...