315 search results - page 10 / 63 » On reducing load store latencies of cache accesses |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
USENIX
1994
13 years 9 months ago
1994
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...