315 search results - page 11 / 63 » On reducing load store latencies of cache accesses |
DATE
2010
IEEE
14 years 20 days ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
EUROPAR
2004
Springer
14 years 29 days ago
2004
Springer
Abstract. Fine-grained software-based distributed shared memory (SWDSM) systems typically maintain coherence with in-line checking code at load and store operations to shared memor...
CC
2004
Springer
14 years 29 days ago
2004
Springer
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Becausepages are the f...