315 search results - page 13 / 63 » On reducing load store latencies of cache accesses |
HPCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
ISLPED
1999
ACM
13 years 12 months ago
1999
ACM
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
CEE
2008
13 years 7 months ago
2008
Web prefetching is an attractive solution to reduce the network resources consumed by Web services as well as the access latencies perceived by Web users. Unlike Web caching, whic...
RTSS
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we present a balanced data replication scheme that provides real-time latency bounds on content retrieval in content distribution networks. Many network applications...