315 search results - page 43 / 63 » On reducing load store latencies of cache accesses |
JEC
2006
13 years 7 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ISCA
2010
IEEE
14 years 21 days ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
PIMRC
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract—Handoff procedure in IEEE 802.11 wireless networks must be accomplished with as little interruption as possible to maintain the required quality of service (QoS). We hav...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...