Sciweavers

315 search results - page 54 / 63
» On reducing load store latencies of cache accesses
Sort
View
MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
14 years 1 months ago
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network. Control messages are forwarded using the ring...
Karin Strauss, Xiaowei Shen, Josep Torrellas
IPPS
2009
IEEE
14 years 2 months ago
Scalable RDMA performance in PGAS languages
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
Montse Farreras, George Almási, Calin Casca...
COMCOM
1998
74views more  COMCOM 1998»
13 years 7 months ago
Using proxies to enhance TCP performance over hybrid fiber coaxial networks
Using cable modems that operate at several hundred times the speed of conventional telephone modems, many cable operators are beginning to offer World Wide Web access and other da...
Reuven Cohen, Srinivas Ramanathan
ASAP
2002
IEEE
105views Hardware» more  ASAP 2002»
14 years 16 days ago
Implications of Programmable General Purpose Processors for Compression/Encryption Applications
With the growth of the Internet and mobile communication industry, multimedia applications form a dominant computer workload. Media workloads are typically executed on Application...
Byeong Kil Lee, Lizy Kurian John
ICS
2000
Tsinghua U.
13 years 11 months ago
Push vs. pull: data movement for linked data structures
As the performance gap between the CPU and main memory continues to grow, techniques to hide memory latency are essential to deliver a high performance computer system. Prefetchin...
Chia-Lin Yang, Alvin R. Lebeck