66 search results - page 11 / 14 » On reducing misspeculations in a pipelined scheduler |
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
ATS
2001
IEEE
14 years 5 days ago
2001
IEEE
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
CF
2005
ACM
13 years 10 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...