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» On the Architecture of System Verification Environments
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DAC
2007
ACM
13 years 11 months ago
Verification Methodologies in a TLM-to-RTL Design Flow
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
Atsushi Kasuya, Tesh Tesfaye
ENTCS
2008
94views more  ENTCS 2008»
13 years 7 months ago
A Formal Model of Memory Peculiarities for the Verification of Low-Level Operating-System Code
This paper presents our solutions to some problems we encountered in an ongoing attempt to verify the micro-hypervisor currently developed within the Robin project. The problems t...
Hendrik Tews, Tjark Weber, Marcus Völp
ICPR
2004
IEEE
14 years 8 months ago
Face Verification System Architecture Using Smart Cards
A smart card based face verification system is proposed in which the feature extraction and decision making is performed on the card. Such an architecture has many privacy and sec...
Josef Kittler, Kieron Messer, Thirimachos Bourlai
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 7 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
PPPJ
2003
ACM
14 years 17 days ago
Supporting interactive invocation of remote services within an integrated programming environment
Building distributed systems is an inherently difficult and complex task. Modern middleware architectures assist developers ding abstractions that hide transport layer functionali...
Bruce Quig, John Rosenberg, Michael Kölling