Sciweavers

287 search results - page 36 / 58
» On the Complexity of Register Coalescing
Sort
View
RTAS
1997
IEEE
13 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
CASES
2007
ACM
13 years 11 months ago
Rethinking custom ISE identification: a new processor-agnostic method
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
Ajay K. Verma, Philip Brisk, Paolo Ienne
EUROCRYPT
2008
Springer
13 years 9 months ago
Isolated Proofs of Knowledge and Isolated Zero Knowledge
We introduce a new notion called -isolated proofs of knowledge ( -IPoK). These are proofs of knowledge where a cheating prover is allowed to exchange up to bits of communication wi...
Ivan Damgård, Jesper Buus Nielsen, Daniel Wi...
MSO
2003
13 years 9 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
CVPR
2000
IEEE
14 years 9 months ago
3-D Model Construction Using Range and Image Data
This paper deals with the automated creation of geometric and photometric correct 3-D models of the world. Those models can be used for virtual reality, tele? presence, digital ci...
Ioannis Stamos, Peter K. Allen