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DAC
2009
ACM
14 years 8 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
CONCUR
2010
Springer
13 years 8 months ago
Modal Logic over Higher Dimensional Automata
Higher dimensional automata (HDA) are a model of concurrency that can express most of the traditional partial order models like Mazurkiewicz traces, pomsets, event structures, or P...
Cristian Prisacariu
ISLPED
2010
ACM
181views Hardware» more  ISLPED 2010»
13 years 6 months ago
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems
 In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-...
Shahin Golshan, Eli Bozorgzadeh, Benjamin Carri&oa...
SENSYS
2004
ACM
14 years 29 days ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
NOSSDAV
2005
Springer
14 years 1 months ago
A formal approach to design optimized multimedia service overlay
Service overlay networks have recently attracted tremendous interests. In this paper, we propose a new integrated framework for specifying services composed of service components ...
Hirozumi Yamaguchi, Khaled El-Fakih, Akihito Hirom...