A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion

As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimization, buffer insertion is indispensable in the physical synthesis flow. Buffering is known to be NP-complete and existing works either explore dynamic programming to compute optimal solution in the worst-case exponential time or design efficient heuristics without performance guarantee. Even if buffer insertion is one of the most studied problems in physical design, whether there is an efficient algorithm with provably good performance still remains unknown. This work settles this open problem. In the paper, the first fully polynomial time approximation scheme for the timing driven minimum cost buffer insertion problem is designed. The new algorithm can approximate the optimal buffering solution within a factor of 1 + running in O(m2 n2 b/ 3 + n3 b2 / ) time for any 0 < < 1, where n is the number of ca...

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Shiyan Hu, Zhuo Li, Charles J. Alpert
• Keywords: Buffer Insertion, Cost Buffer Insertion, DAC 2009, Design Automation, Keywords Buffer Insertion