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» On the Design and Implementation of an Efficient DAA Scheme
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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
13 years 11 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
MOBISYS
2008
ACM
14 years 6 months ago
Improving wireless privacy with an identifier-free link layer protocol
We present the design and evaluation of an 802.11-like wireless link layer protocol that obfuscates all transmitted bits to increase privacy. This includes explicit identifiers su...
Ben Greenstein, Damon McCoy, Jeffrey Pang, Tadayos...
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 11 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen
MATA
2000
Springer
137views Communications» more  MATA 2000»
13 years 10 months ago
Topology Discovery in Ad Hoc Wireless Networks Using Mobile Agents
Extensive research on mobile agents has been rife with the growing interests in network computing. In this paper, we have discussed a mobile multi-agent-based framework to address ...
Romit Roy Choudhury, Somprakash Bandyopadhyay, Kri...

Publication
255views
15 years 5 months ago
Buffer Management and Rate Guarantees for TCP/IP over Satellite-ATM Networks
Future broadband satellite networks will support a variety of service types. Many such systems are being designed with ATM or ATM like technology. A majority of Internet applicatio...
Rohit Goyal, Raj Jain, Mukul Goyal, Sonia Fahmy, B...