115 search results - page 4 / 23 » On the Design of IEEE Compliant Floating Point Units |
ARITH
2005
IEEE
14 years 1 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
ARITH
1999
IEEE
14 years 23 hour ago
1999
IEEE
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
TVLSI
2008
13 years 7 months ago
2008
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...