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COR
2004
106views more  COR 2004»
13 years 8 months ago
Performance analysis of the DAR(1)/D/c priority queue under partial buffer sharing policy
We analyze a multi-server priority queueing system with partial buffer sharing, where the input is a discrete autoregressive process of order 1 (DAR(1)) which is known as a good m...
Gang Uk Hwang, Bong Dae Choi
DAC
2012
ACM
11 years 11 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
IEEEPACT
2009
IEEE
14 years 3 months ago
Using Aggressor Thread Information to Improve Shared Cache Management for CMPs
—Shared cache allocation policies play an important role in determining CMP performance. The simplest policy, LRU, allocates cache implicitly as a consequence of its replacement ...
Wanli Liu, Donald Yeung
PDP
2010
IEEE
14 years 3 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
14 years 25 days ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen