340 search results - page 13 / 68 » On the Interplay of Parallelization, Program Performance, an... |
SAC
2010
ACM
13 years 8 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
SC
2009
ACM
14 years 3 months ago
2009
ACM
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such syste...
ICPP
2003
IEEE
14 years 1 months ago
2003
IEEE
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...