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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 4 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
14 years 4 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
WINE
2009
Springer
178views Economy» more  WINE 2009»
14 years 4 months ago
The Geometry of Truthfulness
We study the geometrical shape of the partitions of the input space created by the allocation rule of a truthful mechanism for multi-unit auctions with multidimensional types and ...
Angelina Vidali
XSYM
2009
Springer
139views Database» more  XSYM 2009»
14 years 4 months ago
A Data Parallel Algorithm for XML DOM Parsing
Abstract. The extensible markup language XML has become the de facto standard for information representation and interchange on the Internet. XML parsing is a core operation perfor...
Bhavik Shah, Praveen Rao, Bongki Moon, Mohan Rajag...
EUROPAR
2009
Springer
14 years 4 months ago
A Case Study of Communication Optimizations on 3D Mesh Interconnects
Optimal network performance is critical to efficient parallel scaling for communication-bound applications on large machines. With wormhole routing, no-load latencies do not increa...
Abhinav Bhatele, Eric J. Bohm, Laxmikant V. Kal&ea...