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EUROPAR
2010
Springer
13 years 9 months ago
Transactional Mutex Locks
Mutual exclusion locks limit concurrency but offer low latency. Software transactional memory (STM) typically has higher latency, but scales well. In this paper we propose transac...
Luke Dalessandro, David Dice, Michael L. Scott, Ni...
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 5 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
RTAS
2006
IEEE
14 years 2 months ago
METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
Multiprocessor systems present serious challenges in the design of real-time systems due to the wider variation of execution time of an instruction sequence compared to a uniproce...
Jae W. Lee, Krste Asanovic
SPAA
2009
ACM
14 years 5 months ago
Optimizing transactions for captured memory
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...
Aleksandar Dragojevic, Yang Ni, Ali-Reza Adl-Tabat...
PPOPP
2009
ACM
14 years 8 months ago
Safe open-nested transactions through ownership
Researchers in transactional memory (TM) have proposed open nesting as a methodology for increasing the concurrency of transactional programs. The idea is to ignore "low-leve...
Kunal Agrawal, I.-Ting Angelina Lee, Jim Sukha