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CGO
2004
IEEE
13 years 11 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 27 days ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
MICRO
1996
IEEE
173views Hardware» more  MICRO 1996»
14 years 4 days ago
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in J...
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei ...
FAST
2003
13 years 9 months ago
Block-Level Security for Network-Attached Disks
We propose a practical and efficient method for adding security to network-attached disks (NADs). In contrast to previous work, our design requires no changes to the data layout ...
Marcos Kawazoe Aguilera, Minwen Ji, Mark Lillibrid...
CHES
2010
Springer
189views Cryptology» more  CHES 2010»
13 years 9 months ago
Quark: A Lightweight Hash
The need for lightweight (that is, compact, low-power, low-energy) cryptographic hash functions has been repeatedly expressed by application designers, notably for implementing RFI...
Jean-Philippe Aumasson, Luca Henzen, Willi Meier, ...