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HPDC
2005
IEEE
14 years 1 months ago
Lerna: an active storage framework for flexible data access and management
In the present paper, we examine the problem of supporting application-specific computation within a network file server. Our objectives are (i) to introduce an easy to use yet ...
Stergios V. Anastasiadis, Rajiv Wickremesinghe, Je...
DATE
2009
IEEE
85views Hardware» more  DATE 2009»
14 years 3 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 2 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
14 years 1 months ago
A new reconfigurable modem architecture for 3G multi-standard wireless communication systems
– The trend in communication systems is towards more rapidly changing specifications with shorter time intervals between updates of existing standards. This results in a coexiste...
Jung-Ho Kim, Dong Sam Ha, Jeffrey H. Reed
GLOBECOM
2007
IEEE
14 years 2 months ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...