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SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
14 years 23 days ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ICPP
1991
IEEE
13 years 11 months ago
B-SYS: A 470-Processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
Richard Hughey, Daniel P. Lopresti
IPPS
2005
IEEE
14 years 1 months ago
Monitoring and Debugging Parallel Software with BCS-MPI on Large-Scale Clusters
Buffered CoScheduled (BCS) MPI is a novel implementation of MPI based on global synchronization of all system activities. BCS-MPI imposes a model where all processes and their com...
Juan Fernández, Fabrizio Petrini, Eitan Fra...
P2P
2008
IEEE
137views Communications» more  P2P 2008»
14 years 1 months ago
Hierarchical Codes: How to Make Erasure Codes Attractive for Peer-to-Peer Storage Systems
Redundancy is the basic technique to provide reliability in storage systems consisting of multiple components. A redundancy scheme defines how the redundant data are produced and...
Alessandro Duminuco, Ernst Biersack
PPOPP
2003
ACM
14 years 23 days ago
Using generative design patterns to generate parallel code for a distributed memory environment
A design pattern is a mechanism for encapsulating the knowledge of experienced designers into a re-usable artifact. Parallel design patterns reflect commonly occurring parallel co...
Kai Tan, Duane Szafron, Jonathan Schaeffer, John A...