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VLSISP
2010
102views more  VLSISP 2010»
13 years 7 months ago
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Fine-grained accelerators have the potential to deliver significant benefits in various platforms for embedded signal processing. Due to the moderate complexity of their targeted o...
Jani Boutellier, Shuvra S. Bhattacharyya, Olli Sil...
TE
2010
102views more  TE 2010»
13 years 3 months ago
An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays
In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a o...
Uwe Meyer-Bäse, G. Alonzo Vera, Anke Meyer-B&...
VLSISP
2008
104views more  VLSISP 2008»
13 years 9 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
ICIP
2003
IEEE
14 years 10 months ago
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
Andrew Laffely, Jian Liang, Russell Tessier, Wayne...
ARCS
2004
Springer
14 years 26 days ago
Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing
: This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamical...
Walter Stechele, Stephan Herrmann, Andreas Herkers...