27 search results - page 3 / 6 » On the Size and Generation of Minimal N-Detection Tests |
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
DSD
2008
IEEE
14 years 1 months ago
2008
IEEE
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
ICSE
2003
IEEE-ACM
14 years 7 months ago
2003
IEEE-ACM
g Test Suites via Operational Abstraction Michael Harder Jeff Mellen Michael D. Ernst MIT Lab for Computer Science 200 Technology Square Cambridge, MA 02139 USA {mharder,jeffm,mern...
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
CCGRID
2010
IEEE
12 years 11 months ago
2010
IEEE
- Scientific workflows have become an integral part of cyberinfrastructure as their computational complexity and data sizes have grown. However, the complexity of the distributed i...