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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 6 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
ASPLOS
2010
ACM
14 years 4 months ago
Power routing: dynamic power provisioning in the data center
Data center power infrastructure incurs massive capital costs, which typically exceed energy costs over the life of the facility. To squeeze maximum value from the infrastructure,...
Steven Pelley, David Meisner, Pooya Zandevakili, T...
PLDI
2009
ACM
14 years 4 months ago
Binary analysis for measurement and attribution of program performance
Modern programs frequently employ sophisticated modular designs. As a result, performance problems cannot be identified from costs attributed to routines in isolation; understand...
Nathan R. Tallent, John M. Mellor-Crummey, Michael...
CCS
2009
ACM
14 years 4 months ago
NISAN: network information service for anonymization networks
Network information distribution is a fundamental service for any anonymization network. Even though anonymization and information distribution about the network are two orthogona...
Andriy Panchenko, Stefan Richter, Arne Rache
LCTRTS
2009
Springer
14 years 4 months ago
Eliminating the call stack to save RAM
Most programming languages support a call stack in the programming model and also in the runtime system. We show that for applications targeting low-power embedded microcontroller...
Xuejun Yang, Nathan Cooprider, John Regehr