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ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 29 days ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein
AAAI
2008
13 years 9 months ago
A General Method for Reducing the Complexity of Relational Inference and its Application to MCMC
Many real-world problems are characterized by complex relational structure, which can be succinctly represented in firstorder logic. However, many relational inference algorithms ...
Hoifung Poon, Pedro Domingos, Marc Sumner
JSAC
1998
136views more  JSAC 1998»
13 years 7 months ago
Concatenated Decoding with a Reduced-Search BCJR Algorithm
—We apply two reduced-computation variants of the BCJR algorithm to the decoding of serial and parallel concatenated convolutional codes. One computes its recursions at only M st...
Volker Franz, John B. Anderson
ICCD
2003
IEEE
130views Hardware» more  ICCD 2003»
14 years 4 months ago
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
RTSS
1996
IEEE
13 years 11 months ago
Reducing the number of clock variables of timed automata
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
Conrado Daws, Sergio Yovine