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» On the Verification of Temporal Properties
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ASYNC
2000
IEEE
94views Hardware» more  ASYNC 2000»
13 years 12 months ago
Formal Verification of Safety Properties in Timed Circuits
Marco A. Peña, Jordi Cortadella, Enric Past...
CAV
1993
Springer
299views Hardware» more  CAV 1993»
13 years 11 months ago
Verification of timing Properties of VHDL
Costas Courcoubetis, Werner Damm, Bernhard Josko