1633 search results - page 56 / 327 » On the Verification of Temporal Properties |
ISCAS
2003
IEEE
14 years 28 days ago
2003
IEEE
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
RV
2010
Springer
13 years 5 months ago
2010
Springer
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict ...
AMAST
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...
IJBC
2010
13 years 2 months ago
2010
In this paper, a discrete version of a reaction-diffusion equation, also known as coupled map lattice (CML), which corresponds to the Turing model of morphogenesis is studied. It i...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...