1633 search results - page 77 / 327 » On the Verification of Temporal Properties |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
The design of a large chip is typically hierarchical
CADE
2005
Springer
14 years 8 months ago
2005
Springer
Abstract. We investigate the computational behaviour of `two-dimensional' propositional temporal logics over (N, <) (with and without the next-time operator ?) that are cap...
LREC
2010
13 years 9 months ago
2010
We present CAVaT, a tool that performs Corpus Analysis and Validation for TimeML. CAVaT is an open source, modular checking utility for statistical analysis of features specific t...
ATVA
2009
Springer
13 years 8 months ago
2009
Springer
Embedded systems often come with constrained memory footprints. It is therefore essential to ensure that software running on such platforms fulfils memory usage specifications at c...
LISP
2002
13 years 7 months ago
2002
Program termination verification is a challenging research subject of significant practical importance. While there is already a rich body of literature on this subject, it is sti...