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MEMOCODE
2006
IEEE
14 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
CASES
2006
ACM
14 years 1 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
CF
2006
ACM
14 years 1 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
BROADNETS
2005
IEEE
14 years 1 months ago
Multi-rate throughput optimization for wireless local area network anomaly problem
— Due to varying wireless channel conditions, the IEEE 802.11 wireless local area network (WLAN) standard supports multiple modulation types to accommodate the tradeoff between d...
Yu-Liang Kuo, Kun-Wei Lai, Frank Yeong-Sung Lin, Y...
BROADNETS
2005
IEEE
14 years 1 months ago
Dual-link failure resiliency through backup link mutual exclusion
— Networks employ link protection to achieve fast recovery from link failures. While the first link failure can be protected using link protection, there are several alternative...
Amit Chandak, Srinivasan Ramasubramanian