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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 11 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 8 months ago
Address Code and Arithmetic Optimizations for Embedded Systems
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, M...
AAAI
2008
13 years 9 months ago
Optimal Metric Planning with State Sets in Automata Representation
This paper proposes an optimal approach to infinite-state action planning exploiting automata theory. State sets and actions are characterized by Presburger formulas and represent...
Björn Ulrich Borowsky, Stefan Edelkamp
MICAI
2007
Springer
14 years 1 months ago
Optimizing Inference in Bayesian Networks and Semiring Valuation Algebras
Previous work on context-specific independence in Bayesian networks is driven by a common goal, namely to represent the conditional probability tables in a most compact way. In th...
Michael Wachter, Rolf Haenni, Marc Pouly
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier