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» On the energy-efficiency of speculative hardware
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FASE
2009
Springer
14 years 2 months ago
HAVE: Detecting Atomicity Violations via Integrated Dynamic and Static Analysis
Abstract. The reality of multi-core hardware has made concurrent programs pervasive. Unfortunately, writing correct concurrent programs is difficult. Atomicity violation, which is ...
Qichang Chen, Liqiang Wang, Zijiang Yang, Scott D....
IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
IEEEPACT
2005
IEEE
14 years 1 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 1 months ago
Why area might reduce power in nanoscale CMOS
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
Paul Beckett, S. C. Goldstein