415 search results - page 81 / 83 » On the energy-efficiency of speculative hardware |
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
MICRO
1996
IEEE
13 years 11 months ago
1996
IEEE
Much of the previous work on modulo scheduling has targeted numeric programs, in which, often, the majority of the loops are well-behaved loop-counter-based loops without early ex...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
SIGMOD
2008
ACM
14 years 7 months ago
2008
ACM
Online Transaction Processing (OLTP) databases include a suite of features -- disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading ...