ITC 1998 - PDF Preprint Papers

ITC 1998 International Test Conference

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ITC
1998
IEEE

174views Hardware» more ITC 1998»

High volume microprocessor test escapes, an analysis of defects our tests are missing

14 years 5 months ago

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This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...

Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong

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Id	Views	Title	Status

1	174	High volume microprocessor test escapes, an analysis of defects our tests are missing	claim
2	126	A comprehensive approach to the partial scan problem using implicit state enumeration	claim
3	120	Test generation in VLSI circuits for crosstalk noise	claim
4	117	On applying non-classical defect models to automated diagnosis	claim
5	114	BETSY: synthesizing circuits for a specified BIST environment	claim
6	104	Built-in self-test of FPGA interconnect	claim
7	95	Native mode functional test generation for processors with applications to self test and design validation	claim
8	94	Probabilistic mixed-model fault diagnosis	claim
9	94	A method of serial data jitter analysis using one-shot time interval measurements	claim
10	94	Testing embedded-core based system chips	claim
11	91	DFT guidance through RTL test justification and propagation analysis	claim
12	89	Detecting resistive shorts for CMOS domino circuits	claim
13	86	An introduction to area array probing	claim
14	82	A high speed and area efficient on-chip analog waveform extractor	claim
15	79	An almost full-scan BIST solution-higher fault coverage and shorter test application time	claim
16	77	Deterministic BIST with multiple scan chains	claim
17	73	Maximization of power dissipation under random excitation for burn-in testing	claim
18	72	Modeling the unknown! Towards model-independent fault and error diagnosis	claim
19	71	A structured and scalable mechanism for test access to embedded reusable cores	claim
20	69	A performance analysis system for MEMS using automated imaging methods	claim
21	68	A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits	claim
22	66	A novel combinational testability analysis by considering signal correlation	claim
23	65	Consequences of port restrictions on testing two-port memories	claim
24	65	Failure modes for stiction in surface-micromachined MEMS	claim
25	64	A fault injection environment for microprocessor-based boards	claim
26	61	Test session oriented built-in self-testable data path synthesis	claim
27	60	Semiconductor manufacturing process monitoring using built-in self-test for embedded memories	claim
28	59	Stimulus generation for built-in self-test of charge-pump phase-locked loops	claim
29	58	Novel optical probing technique for flip chip packaged microprocessors	claim

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