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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 5 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
ICS
2009
Tsinghua U.
13 years 5 months ago
Refereeing conflicts in hardware transactional memory
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
Arrvindh Shriraman, Sandhya Dwarkadas
JSA
2010
173views more  JSA 2010»
13 years 2 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
PDP
2011
IEEE
12 years 11 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
EDBT
2011
ACM
199views Database» more  EDBT 2011»
12 years 11 months ago
Predicting completion times of batch query workloads using interaction-aware models and simulation
A question that database administrators (DBAs) routinely need to answer is how long a batch query workload will take to complete. This question arises, for example, while planning...
Mumtaz Ahmad, Songyun Duan, Ashraf Aboulnaga, Shiv...