Sciweavers

131 search results - page 3 / 27
» On the k-additive Core of Capacities
Sort
View
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
12 years 7 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
CATS
2008
13 years 8 months ago
The Core Concept for 0/1 Integer Programming
In this paper we examine an extension of the core concept for the 0/1 Multidimensional Knapsack Problem (MKP) towards general 0/1 Integer Programming (IP) by allowing negative pro...
Samuel Huston, Jakob Puchinger, Peter J. Stuckey
EH
2003
IEEE
135views Hardware» more  EH 2003»
14 years 21 days ago
Towards Evolvable IP Cores for FPGAs
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
Lukás Sekanina
ISIPTA
1999
IEEE
13 years 11 months ago
Totally Monotone Core and Products of Monotone Measures
Several approaches to the product of non-additive monotone measures or capacities are discussed and a new approach is proposed. It starts with the Mobius product 2 of totally mono...
Dieter Denneberg
HIPEAC
2007
Springer
14 years 1 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...