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» On the optimality of the neighbor-joining algorithm
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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2003
IEEE
117views Hardware» more  ICCAD 2003»
14 years 4 months ago
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...
Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
FPGA
2010
ACM
359views FPGA» more  FPGA 2010»
14 years 4 months ago
Towards scalable placement for FPGAs
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...
Huimin Bian, Andrew C. Ling, Alexander Choong, Jia...
EUROGRAPHICS
2010
Eurographics
14 years 2 months ago
Articulated Billboards for Video-based Rendering
We present a novel representation and rendering method for free-viewpoint video of human characters based on multiple input video streams. The basic idea is to approximate the art...
Marcel Germann, Alexander Hornung, Richard Keiser,...
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