184 search results - page 32 / 37 » On the power of hardware transactional memory to simplify me... |
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Transiently powered computing devices such as RFID tags, kinetic energy harvesters, and smart cards typically rely on programs that complete a task under tight time constraints be...
IWOMP
2007
Springer
14 years 1 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
CIKM
2001
Springer
13 years 11 months ago
2001
Springer
We explore in this paper an effective sliding-window filtering (abbreviatedly as SWF) algorithm for incremental mining of association rules. In essence, by partitioning a transact...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...