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    FPGA
    2006
    ACM
    111views FPGA» more  FPGA 2006»
    FPGA clock network architecture: flexibility vs. area and power
    14 years 1 months ago
    FPGA clock network architecture: flexibility vs. area and power
    Download  www.ece.ubc.ca
    This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
    Julien Lamoureux, Steven J. E. Wilton
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    TRETS
    2008
    42views more  TRETS 2008»
    On the trade-off between power and flexibility of FPGA clock networks
    13 years 9 months ago
    On the trade-off between power and flexibility of FPGA clock networks
    Download  www.ece.ubc.ca
    Julien Lamoureux, Steven J. E. Wilton
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    CSB
    2004
    IEEE
    108views Bioinformatics» more  CSB 2004»
    Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
    14 years 1 months ago
    Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
    Download  www.uprh.edu
    Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
    Terrence S. T. Mak, Kai-Pui Lam
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    ANCS
    2008
    ACM
    183views Computer Networks» more  ANCS 2008»
    Low power architecture for high speed packet classification
    13 years 11 months ago
    Low power architecture for high speed packet classification
    Download  cial.csie.ncku.edu.tw
    Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
    Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
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    JSA
    2010
    158views more  JSA 2010»
    Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
    13 years 4 months ago
    Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
    Download  hal.inria.fr
    The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
    Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
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