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» On the vertices of the k-additive core
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ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
13 years 11 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar
HICSS
2006
IEEE
140views Biometrics» more  HICSS 2006»
14 years 1 months ago
Alternative Pathway to Electricity Market Reform: A Risk-Management Approach
— An evolutionary “Third Way” approach for restructuring the electricity industry is proposed, striking a balance between the extremes of vertical integration and direct libe...
Hung-po Chao, Shmuel S. Oren, Robert Wilson
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
13 years 11 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 21 days ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 20 days ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar