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» On two-step routing for FPGAS
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NETWORKING
2000
13 years 8 months ago
Computing Blocking Probabilities in Multi-class Wavelength Routing Networks
We present an approximate analytical method to compute efficiently the call blocking probabilities in wavelength routing networks with multiple classes of calls. The model is fairl...
Sridhar Ramesh, George N. Rouskas, Harry G. Perros
IPPS
1998
IEEE
13 years 11 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 11 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 7 days ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
DATE
2003
IEEE
69views Hardware» more  DATE 2003»
14 years 12 hour ago
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
Ulrich Seidl, Klaus Eckl, Frank M. Johannes