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» On two-step routing for FPGAS
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FPL
2006
Springer
161views Hardware» more  FPL 2006»
13 years 10 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
TVLSI
2008
111views more  TVLSI 2008»
13 years 6 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
SLIP
2005
ACM
14 years 8 days ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
TVLSI
2010
13 years 1 months ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
13 years 10 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan