66 search results - page 11 / 14 » On-Chip Inductance in X Architecture Enabled Design |
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
GPGPUs have recently emerged as powerful vehicles for generalpurpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from N...
EUROPAR
2010
Springer
13 years 8 months ago
2010
Springer
Mutual exclusion locks limit concurrency but offer low latency. Software transactional memory (STM) typically has higher latency, but scales well. In this paper we propose transac...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
FPGA
2010
ACM
13 years 7 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...