229 search results - page 21 / 46 » On-Chip Test Generation Using Linear Subspaces |
EOR
2006
13 years 7 months ago
2006
In this paper a hybrid algorithm to solve Irregular Strip Packing problems is presented. The metaheuristic simulated annealing is used to guide the search over the solution space ...
DSP
2006
13 years 7 months ago
2006
We describe the use of the discrete wavelet transform (DWT) for non-parametric linear time-invariant system identification. Identification is achieved by using a test excitation t...
ICML
2010
IEEE
13 years 8 months ago
2010
IEEE
Dimension reduction is popular for learning predictive models in high-dimensional spaces. It can highlight the relevant part of the feature space and avoid the curse of dimensiona...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
F0 is an acoustic feature that varies largely from one speaker to another. F0 is characterized by a discontinuity in the transition between voiced and unvoiced sounds that present...