229 search results - page 29 / 46 » On-Chip Test Generation Using Linear Subspaces |
GECCO
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents the Real-coded Genetic Algorithms for high-dimensional ill-scaled structures, what is called, the ktablet structure. The k-tablet structure is the landscape th...
CVPR
2007
IEEE
14 years 9 months ago
2007
IEEE
We propose a novel algorithm for segmenting multiple motions of different types from point correspondences in multiple affine or perspective views. Since point trajectories associ...
GD
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. A graph is planar if and only if it does not contain a Kuratowski subdivision. Hence such a subdivision can be used as a witness for non-planarity. Modern planarity testi...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ISCAS
2002
IEEE
14 years 18 days ago
2002
IEEE
We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors...