Sciweavers

229 search results - page 5 / 46
» On-Chip Test Generation Using Linear Subspaces
Sort
View
INTERSPEECH
2010
13 years 2 months ago
Reduction of broadband noise in speech signals by multilinear subspace analysis
A new noise reduction method for speech signals is proposed in this paper. The method is based upon the N-mode singular value decomposition algorithm, which exploits the multiline...
Yusuke Sato, Tetsuya Hoya, Hovagim Bakardjian, And...
ATS
2003
IEEE
105views Hardware» more  ATS 2003»
14 years 28 days ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
14 years 1 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba
TIFS
2008
157views more  TIFS 2008»
13 years 7 months ago
Subspace Approximation of Face Recognition Algorithms: An Empirical Study
We present a theory for constructing linear subspace approximations to face-recognition algorithms and empirically demonstrate that a surprisingly diverse set of face-recognition a...
Pranab Mohanty, Sudeep Sarkar, Rangachar Kasturi, ...
ICPR
2004
IEEE
14 years 8 months ago
Recognition of Expression Variant Faces Using Weighted Subspaces
In the past decade or so, subspace methods have been largely used in face recognition ? generally with quite success. Subspace approaches, however, generally assume the training d...
Aleix M. Martínez, Yongbin Zhang