704 search results - page 2 / 141 » On-chip logic minimization |
MICRO
2005
IEEE
14 years 3 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
TCAD
2008
13 years 9 months ago
2008
Abstract--This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an o...
FCCM
2002
IEEE
14 years 2 months ago
2002
IEEE
We examine the energy savings possible by re-mapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commerci...
DT
2002
13 years 9 months ago
2002
ETS
2011
IEEE
12 years 9 months ago
2011
IEEE
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...