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ISCAPDCS
2004
13 years 10 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
DCC
2010
IEEE
13 years 8 months ago
A tight asymptotic bound on the size of constant-weight conflict-avoiding codes
In the study of multiple-access in the collision channel, conflict-avoiding code is used to guarantee that each transmitting user can send at least one packet successfully in the w...
Kenneth W. Shum, Wing Shing Wong
ICAC
2008
IEEE
14 years 3 months ago
Towards a Self-Configurable Weather Research and Forecasting System
Current weather forecast and visualization systems lack the scalability to support numerous customized requests for weather research and forecasting, especially at the time of nat...
Khalid Saleem, Seyed Masoud Sadjadi, Shu-Ching Che...
GECCO
2004
Springer
14 years 2 months ago
On the Choice of the Population Size
Abstract. Evolutionary Algorithms (EAs) are population-based randomized optimizers often solving problems quite successfully. Here, the focus is on the possible effects of changin...
Tobias Storch
ICC
2007
IEEE
14 years 3 months ago
Reducing the Size of Rule Set in a Firewall
— A firewall’s complexity is known to increase with the size of its rule set. Complex firewalls are more likely to have configuration errors which cause security loopholes. ...
MyungKeun Yoon, Shigang Chen, Zhan Zhang