In enterprise and data center networks, the scalability of the data plane becomes increasingly challenging as forwarding tables and link speeds grow. Simply building switches with...
A 4KB page size has been used for Virtual Memory since the sixties. In fact, today, the most common page size is still 4KB. Choosing a page size is finding the middle ground betwe...
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
: We study the weight distribution and list-decoding size of Reed-Muller codes. Given a weight parameter, we are interested in bounding the number of Reed-Muller codewords with a w...