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MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
15 years 9 months ago
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...
LCTRTS
2007
Springer
15 years 8 months ago
Frequency-aware energy optimization for real-time periodic and aperiodic tasks
Energy efficiency is an important factor in embedded systems design. We consider an embedded system with a dynamic voltage scaling (DVS) capable processor and its system-wide pow...
Xiliang Zhong, Cheng-Zhong Xu
AIPS
2006
15 years 3 months ago
Planning for PDDL3 - An OCSP Based Approach
Recent research in AI Planning is focused on improving the quality of the generated plans. PDDL3 incorporates hard and soft constraints on goals and the plan trajectory. Plan traj...
Bharat Ranjan Kavuluri, Naresh Babu Saladi, Deepak...
120
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CORR
2008
Springer
105views Education» more  CORR 2008»
15 years 2 months ago
On Full Diversity Space-Time Block Codes with Partial Interference Cancellation Group Decoding
In this paper, we propose a partial interference cancellation (PIC) group decoding strategy/scheme for linear dispersive space-time block codes (STBC) and a design criterion for th...
Xiaoyong Guo, Xiang-Gen Xia
JAIR
2006
179views more  JAIR 2006»
15 years 2 months ago
The Fast Downward Planning System
Fast Downward is a classical planning system based on heuristic search. It can deal with general deterministic planning problems encoded in the propositional fragment of PDDL2.2, ...
Malte Helmert