Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
This paper is about optimizing Grid application setup by allowing a user to configure a Grid application on her own PC and thereafter migrating the entire application onto the Gri...
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...
There is a debate regarding whether motor memory is stored in the cerebellar cortex, or the cerebellar nuclei, or both. Memory may be acquired in the cortex and then be transferred...